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M28W320FSU M28W640FSU
32Mbit (2Mb x16) and 64Mbit (4Mb x16) 3V Supply, Uniform Block, Secure Flash Memories
FEATURES SUMMARY

SUPPLY VOLTAGE - VDD = 2.7V to 3.6V Core Power Supply - VDDQ= 2.7V to 3.6V for Input/Output - VPP = 12V for fast Program (optional) ACCESS TIME: 70ns PROGRAMMING TIME: - 10s typical - Double Word Programming Option - Quadruple Word Programming Option COMMON FLASH INTERFACE UNIFORM BLOCKS 64-KWord UNIFORM MEMORY BLOCKS - M28W320FSU: 32 Blocks - M28W640FSU: 64 Blocks HARDWARE PROTECTION - VPP Pin for Write protect of All Blocks SECURITY FEATURES - 128 bit User-programmable OTP segment - 64 bit Unique Device Identifier - KRYPTO Features: Modify Protection, Read Protection, Device Authentication AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Codes: M28W320FSU: 880Ch, M28W640FSU: 8857h PACKAGE - Compliant with Lead-Free Soldering Processes - Lead-Free Version
Figure 1. Package
BGA
TBGA64 (ZA) 10 x 13mm
May 2005
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M28W320FSU, M28W640FSU
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Figure 3. Table 1. Figure 4. Figure 5. Figure 6. M28W320FSU Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 M28W640FSU Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 M28W320FSU and M28W640FSU Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Address Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 HARDWARE PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VPP VPPLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SECURITY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6. Read Protection Register and Protection Register Lock . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 17 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 10. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 11. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 12. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 9. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 10.Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 14. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 11.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 15. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 12.Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 16. Power-Up and Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 13.TBGA64 - 10x13 active ball array, 1mm pitch, Bottom View Package Outline . . . . . . . . 29 Table 17. TBGA64 - 10x13 active ball array, 1mm pitch, Package Mechanical Data . . . . . . . . . . . 29
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PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 19. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 20. Block Addresses, M28W320FSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 21. Block Addresses, M28W640FSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 22. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 23. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 24. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 25. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 26. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 27. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 14.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 15.Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 16.Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 17.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 42 Figure 18.Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 19.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 20.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 45 APPENDIX D.COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE. . . . . . . . 46 Table 28. Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 29. Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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SUMMARY DESCRIPTION
The M28W320FSU and the M28W640FSU are 32 Mbit (2Mbit x 16) and 64 Mbit (4Mbit x 16) Secure Flash memories. The devices can be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 2.7V to 3.6V VDD supply for the circuitry and a 2.7V to 3.6V VDDQ supply for the Input/Output pins. An optional 12V VPP power supply is provided to speed up customer programming. The M28W320FSU and M28W640FSU feature 32 Mbits and 64 Mbits respectively and are divided into thirty-two and sixty-four 64-KWord Uniform blocks, respectively. Refer to Figure 5. for a detailed description of the devices memory architecture and map. All devices are equipped with hardware and software block protection features to avoid unwanted program/erase (modify) or read of the Flash memory content: Hardware Protection: - When VPP VPPLK all blocks are protected against program or erase. Software Protection thanks to KRYPTO Security Features: - Modify Protection: volatile and nonvolatile. - Read Protection. The KRYPTO Security features are described in a dedicated Application Note. Please contact STMicroelectronics for further details. Two registers are available for protection purpose: The Protection Register The KRYPTO Protection Register. The Protection Register is a 192 bit Protection Register to increase the protection of a system design. The Protection Register is divided into a 64 bit segment and a 128 bit segment. The 64 bit segment contains a unique device number written by ST, while the second one is one-time-programmable by the user. The user programmable segment can be permanently protected. Figure 6., shows the Protection Register Memory Map. The KRYPTO Protection Register is used to manage the Modify and Read protection modes. It also features a Device Authentication mechanism. The KRYPTO Protection Register is described in a dedicated Application Note. Please contact STMicroelectronics for further details. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. All the devices are offered in a TBGA64 (10 x 13mm) package. In addition to the standard version, the package is also available in Lead-free version, in compliance with JEDEC Std J-STD020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. The package is compliant with Lead-free soldering processes. All devices are supplied with all the bits erased (set to '1').
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Figure 2. M28W320FSU Logic Diagram
VDD VDDQ VPP 21 A0-A20 W E M28W320FSU G RP G RP DQ0-DQ15 16 A0-A21 W E M28W640FSU DQ0-DQ15 22
Figure 3. M28W640FSU Logic Diagram
VDD VDDQ VPP 16
VSS
AI10659
VSS
AI10660
Table 1. Signal Names
M28W320FSU A0-A20 DQ0-DQ15 E G W RP VDD VDDQ VPP VSS NC M28W640FSU A0-A21 Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Reset Core Power Supply Power Supply for Input/Output Optional Supply Voltage for Fast Program & Erase Ground Not Connected Internally Signal Names
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Figure 4. TBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
A0
A5
A7
VPP
A12
VDD
A17
A21
B
A1
VSS
A8
E
A13
NC
A18
NC
C
A2
A6
A9
A11
A14
NC
A19
A20
D
A3
A4
A10
RP
NC
NC
A15
A16
E
DQ8
DQ1
DQ9
DQ3
DQ4
NC
DQ15
NC
F
NC
DQ0
DQ10
DQ11
DQ12
NC
NC
G
G
NC
NC
DQ2
VDDQ
DQ5
DQ6
DQ14
W
H
NC
NC
VDD
VSSQ
DQ13
VSS
DQ7
NC
AI09910b
Note: 1. The above figure gives the TBGA connections for M28W640FSU. On M28W320FSU, A21 is NC.
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Figure 5. M28W320FSU and M28W640FSU Block Addresses
M28W320FSU Block Addresses M28W640FSU Block Addresses
1FFFFFh 64 KWords 1F0000h 1EFFFFh 64 KWords 1E0000h Total of 32 1 Mbit Uniform Blocks
3FFFFFh 64 KWords 3F0000h 3EFFFFh 64 KWords 3E0000h Total of 64 1 Mbit Uniform Blocks
01FFFFh 64 KWords 010000h 00FFFFh 64 KWords 000000h
01FFFFh 64 KWords 010000h 00FFFFh 64 KWords 000000h
AI10661
Note: 1. Also see APPENDIX A., Tables 21 and 20 for a full listing of the Block Addresses.
Figure 6. Protection Register Memory Map
PROTECTION REGISTER 8Ch User Programmable OTP 85h 84h Unique device number 81h 80h Protection Register Lock 1 0
AI05520b
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M28W320FSU, M28W640FSU
SIGNAL DESCRIPTIONS
See Figures 2 and 3, Logic Diagrams and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs. The Address Inputs select the cells in the memory array to access during Bus Read operations. Address Inputs range from A0 to A20 for the M28W320FSU. The M28W640FSU has an additional A21 address line. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. Output Enable (G). The Output Enable controls data outputs during the Bus Read operation of the memory. Write Enable (W). The Write Enable controls the Bus Write operation of the memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. Reset (RP). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is minimized. After Reset all blocks are in the Locked state. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is required to ensure valid data outputs. VDD Supply Voltage. VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQ Supply Voltage. VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply. VPP Program Supply Voltage. VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. The Supply Voltage VDD and the Program Supply Voltage VPP can be applied in any order. If VPP is kept in a low voltage range (0V to 3.6V) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see Table 12., DC Characteristics, for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect on Program or Erase. If VPP is set to VPPH, it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed (see Table 14. and Table 15.). A Quadruple Word Program command will be ignored if VPP is not set to VPPH while a Double Word Program can be performed even if VPP is set to VDD. VSS Ground. VSS is the reference for all voltage measurements. Note: Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1F capacitor close to the pin. See Figure 8., AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents.
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BUS OPERATIONS
There are six standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2., Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figure 9., Read AC Waveforms, and Table 13., Read AC Characteristics, for details of when the output becomes valid. Read mode is the default state of the device when exiting Reset or after power-up. Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. See Figure 10. and Figure 11., Write AC Waveforms, and Table 14. and Table 15., Write AC Table 2. Bus Operations
Operation Bus Read Bus Write Output Disable Standby Reset E VIL VIL VIL VIH X G VIL VIH VIH X X W VIH VIL VIH X X RP VIH VIH VIH VIH VIL VPP Don't Care VDD or VPPH Don't Care Don't Care Don't Care DQ0-DQ15 Data Output Data Input Hi-Z Hi-Z Hi-Z
Characteristics, for details of the timing requirements. Output Disable. The data outputs are high impedance when the Output Enable is at VIH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable is at VIH and the device is in read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished. Automatic Standby. Automatic Standby provides a low power consumption state during Read mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity even if Chip Enable is Low, VIL, and the supply current is reduced to IDD1. The data Inputs/Outputs will still output data if a bus Read operation is in progress. Reset. During Reset mode when Output Enable is Low, VIL, the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid.
Note: X = VIL or VIH, VPPH = 12V 5%.
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HARDWARE PROTECTION
All devices feature hardware protection. Refer to SIGNAL DESCRIPTIONS section for a detailed description of these signals. VPP VPPLK. The VPP pin protects all the memory blocks from program and erase operations. Refer to SIGNAL DESCRIPTIONS section for a detailed description of these signals.
SECURITY FEATURES
The M28W320FSU and M28W640FSU are equipped with KRYPTO Security features performing software protection. They allow any block to be protected from program/erase or read operations: Modify Protection including Volatile Block Lock/Unlock, Non-Volatile Block Modify Protection, Non-Volatile Password Modify Protection and Irreversible Protection. Read Protection. The KRYPTO features (Modify Protection mode, Read Protection mode and Device Authentication mechanism) are not described in this Datasheet. For further details concerning these additional protection modes please contact ST Sales Offices. The devices also feature a 64 bit Unique Device Identifier and a 128 bit user-programmable OTP segment (see Figure 6., Protection Register Memory Map and Protection Register Program Command).
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COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time, to monitor the progress of the operation, or the Program/ Erase states. See Table 3., Command Codes, for a summary of the commands and see APPENDIX D., Table 28., Write State Machine Current/Next, sheet 1 of 2., for a summary of the Command Interface. The Command Interface is reset to Read mode when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will reset the device to Read mode. Refer to Table 4., Commands, in conjunction with the text descriptions below. Read Memory Array Command The Read command returns the memory to its Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will read the addressed location and output the data. When a device Reset occurs, the memory defaults to Read mode. Read Status Register Command The Status Register indicates when a program or erase operation is complete and the success or failure of the operation itself. Issue a Read Status Register command to read the Status Register's contents. Subsequent Bus Read operations read the Status Register at any address, until another command is issued. See Table 8., Status Register Bits, for details on the definitions of the bits. The Read Status Register command may be issued at any time, even during a Program/Erase operation. Any Read attempt during a Program/ Erase operation will automatically output the content of the Status Register. Read Electronic Signature Command The Read Electronic Signature command reads the Manufacturer and Device Codes, and the Protection Register. The Read Electronic Signature command consists of one write cycle, a subsequent read will output the Manufacturer Code, the Device Code and the Protection Register. See Tables 5, and 6 for the valid address. Table 3. Command Codes
Hex Code
01h
Command Block Lock confirm Program Erase Double Word Program Program Clear Status Register Quadruple Word Program Read Status Register Read Electronic Signature Read CFI Query Program/Erase Suspend Protection Register Program Program/Erase Resume Read Memory Array
10h 20h 30h 40h 50h 56h 70h 90h 98h B0h C0h D0h FFh
Read CFI Query Command The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area, allowing programming equipment or applications to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See APPENDIX B., COMMON FLASH INTERFACE (CFI), Tables 22, 23, 24, 25, 26 and 27 for details on the information contained in the Common Flash Interface memory area. Block Erase Command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. The first bus cycle sets up the Erase command. The second latches the block address in the internal state machine and starts the Program/ Erase Controller.
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If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. During Erase operations the memory will accept the Read Status Register command and the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are given in Table 7., Program, Erase Times and Program/Erase Endurance Cycles. See APPENDIX C., Figure 18., Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Erase command. Program Command The memory array can be programmed word-byword. Two bus write cycles are required to issue the Program Command. The first bus cycle sets up the Program command. The second latches the Address and the Data to be written and starts the Program/Erase Controller. During Program operations the memory will accept the Read Status Register command and the Program/Erase Suspend command. Typical Program times are given in Table 7., Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See APPENDIX C., Figure 14., Program Flowchart and Pseudo Code, for the flowchart for using the Program command. Double Word Program Command This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. The Double Word Program command can be issued either with VPP set to VPPH or to VDD. Three bus write cycles are necessary to issue the Double Word Program command. The first bus cycle sets up the Double Word Program Command. The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See APPENDIX C., Figure 15., Double Word Program Flowchart and Pseudo Code for the flowchart for using the Double Word Program command. Quadruple Word Program Command This feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel.The four words must differ only for the addresses A0 and A1. A Quadruple word Program command will be ignored if VPP is not set to VPPH. Five bus write cycles are necessary to issue the Quadruple Word Program command. The first bus cycle sets up the Quadruple Word Program Command. The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written. The fourth bus cycle latches the Address and the Data of the third word to be written. The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See APPENDIX C., Figure 16., Quadruple Word Program Flowchart and Pseudo Code, for the flowchart for using the Quadruple Word Program command. Clear Status Register Command The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to `0'. One bus write cycle is required to issue the Clear Status Register command. The bits in the Status Register do not automatically return to `0' when a new Program or Erase command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase
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command and pause the Program/Erase controller. During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array, Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Program, Double Word Program, Quadruple Word Program, Block Lock, or Protection Program commands will also be accepted. The block being erased may be protected by issuing the Block Protect, Block Lock or Protection Program commands. When the Program/Erase Resume command is issued the operation will complete. Only the blocks not being erased may be read or programmed correctly. During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to VIH. Program/Erase is aborted if Reset turns to VIL. See APPENDIX C., Figure 17., Program Suspend & Resume Flowchart and Pseudo Code, and Figure 19., Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the Program/Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the command. Once the command is issued subsequent Bus Read operations read the Status Register. See APPENDIX C., Figure 17., Program Suspend & Resume Flowchart and Pseudo Code, and Figure 19., Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the Program/Erase Resume command. Protection Register Program Command The Protection Register Program command is used to Program the 128 bit user One-Time-Programmable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to `1'. The user can only program the bits to `0'. Two write cycles are required to issue the Protection Register Program command. The first bus cycle sets up the Protection Register Program command. The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure 6., Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register is not reversible. The Protection Register Program cannot be suspended.
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Table 4. Commands
Cycles Bus Write Operations 1st Cycle Op. Add Data
X X X X X X X FFh 70h 90h 98h 20h
Commands
2nd Cycle Op. Add Data
Read Read RA X RD SRD IDh QD D0h PD PD1
3rd Cycle
4th Cycle Add Data
5th Cycle Op. Add Data
Op. Add Data Op.
Read Memory Array Read Status Register Read Electronic Signature Read CFI Query Erase Program Double Word Program(3) Quadruple Word Program(4) Clear Status Register Program/Erase Suspend Program/Erase Resume Protection Register Program
1+ Write 1+ Write 1+ Write 1+ Write 2 2 3 Write Write Write
Read SA(2) Read Write QA BA PA
40h or Write 10h 30h
Write PA1
Write
PA2
PD2
5 1 1 1 2
Write Write Write Write Write
X X X X X
56h 50h B0h D0h C0h
Write PA1
PD1
Write
PA2
PD2 Write
PA3
PD3 Write
PA4
PD4
Write PRA
PRD
Note: 1. X = Don't Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device Code), QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data. 2. The signature addresses are listed in Tables 5 and 6. 3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0. 4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
Table 5. Read Electronic Signature
Code Manufacture Code M28W320FSU Device Code M28W640FSU VIL VIL VIH VIH VIL 0 Don't Care 57h 88h
Note: 1. RP = VIH. 2. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU.
Device
E VIL VIL
G VIL VIL
W VIH VIH
A0 VIL VIH
A1 VIL VIL
A2-A7 0 0
A8-A20 A8-A21(2) Don't Care Don't Care
DQ0-DQ7 20h 0Ch
DQ8-DQ15 00h 88h
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Table 6. Read Protection Register and Protection Register Lock
Word Lock Unique ID 0 Unique ID 1 Unique ID 2 Unique ID 3 OTP 0 OTP 1 OTP 2 OTP 3 OTP 4 OTP 5 OTP 6 OTP 7 E VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL G VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL W VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH A0-A7 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch A8-A21(1) Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care DQ0 0 ID data ID data ID data ID data OTP data OTP data OTP data OTP data OTP data OTP data OTP data OTP data DQ1 OTP Prot. data ID data ID data ID data ID data OTP data OTP data OTP data OTP data OTP data OTP data OTP data OTP data DQ2 0 ID data ID data ID data ID data OTP data OTP data OTP data OTP data OTP data OTP data OTP data OTP data DQ3-DQ7 DQ8-DQ15 00h ID data ID data ID data ID data OTP data OTP data OTP data OTP data OTP data OTP data OTP data OTP data 00h ID data ID data ID data ID data OTP data OTP data OTP data OTP data OTP data OTP data OTP data OTP data
Note: 1. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU.
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Table 7. Program, Erase Times and Program/Erase Endurance Cycles
M28W320FSU, M28W640FSU Parameter Word Program Double Word Program Quadruple Word Program Using Word Program command Block Program Using Double Word Program command Using Quadruple Word Program command Block Erase Program/Erase Cycles (per Block) Data Retention Test Conditions Min VPP = VDD VPP = VPPH or VPP = VDD VPP = VPPH VPP = VDD VPP = VPPH or VPP = VDD VPP = VPPH VPP =VPPH or VPP = VDD 100,000 20 Typ 10 10 10 0.64 0.32 Max 200 200 200 s s s s s Unit
5
0.16
s
1
10
s cycles years
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STATUS REGISTER
The Status Register provides information on the current or previous Program or Erase operation. The various bits convey information and errors on the operation. To read the Status register the Read Status Register command can be issued, refer to Read Status Register Command section. To output the contents, the Status Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to VIH. Either Chip Enable or Output Enable must be toggled to update the latched data. Bus Read operations from any address always read the Status Register during Program and Erase operations. The bits in the Status Register are summarized in Table 8., Status Register Bits. Refer to Table 8. in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPP Status and Block Lock Status bits should be tested for errors. Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that an Erase operation has been suspended or is going to be suspended. When the Erase Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 7 is set within 30s of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. Erase Status (Bit 5). The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to `1'), the Program/ Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4). The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. VPP Status (Bit 3). The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to `0'), the voltage on the VPP pin was sampled at a valid voltage; when the VPP Status bit is High (set to `1'), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed. Once set High, the VPP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status (Bit 2). The Program Suspend Status bit indicates that a Program operation has been suspended. When the Program Suspend Status bit is High (set to `1'), a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Pro-
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gram/Erase Controller Status bit is High (Program/ Erase Controller inactive). Bit 2 is set within 5s of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to `1'), a Program or Erase operation has been attempted on a locked block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value must be masked. Note: Refer to APPENDIX C., FLOWCHARTS AND PSEUDO CODES, for using the Status Register.
Table 8. Status Register Bits
Bit 7 P/E.C. Status '0' '1' 6 Erase Suspend Status '0' '1' 5 Erase Status '0' '1' 4 Program Status '0' '1' 3 VPP Status '0' '1' 2 Program Suspend Status '0' '1' 1 0 Block Protection Status '0' Reserved No operation to protected blocks In Progress or Completed Program/Erase on protected Block, Abort Program Success VPP Invalid, Abort VPP OK Suspended Erase Success Program Error In progress or Completed Erase Error Busy Suspended Name Logic Level '1' Ready Definition
Note: Logic level '1' is High, '0' is Low.
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MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 9. Absolute Maximum Ratings
Value Symbol TA TBIAS TSTG TLEAD VIO VDD, VDDQ VPP Parameter Min Ambient Operating Temperature (1) Temperature Under Bias Storage Temperature Lead Temperature during Soldering Input or Output Voltage Supply Voltage Program Voltage - 0.6 - 0.6 - 0.6 - 40 - 40 - 55 Max 85 125 155
(2)
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Unit C C C C V V V
VDDQ+0.6 4.1 13
Note: 1. Depends on range. 2. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
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DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 10., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 10. Operating and AC Measurement Conditions
M28W320FSU, M28W640FSU Parameter Min VDD Supply Voltage VDDQ Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 0 to VDDQ VDDQ/2 2.7 2.7 -40 50 5 70 Units Max 3.6 3.6 85 V V C pF ns V V
Figure 7. AC Measurement I/O Waveform
Figure 8. AC Measurement Load Circuit
VDDQ
VDDQ VDDQ/2 0V
AI00610
VDDQ VDD 25k DEVICE UNDER TEST 0.1F 0.1F CL 25k
CL includes JIG capacitance
AI00609C
Table 11. Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: Sampled only, not 100% tested.
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Table 12. DC Characteristics
Symbol ILI ILO IDD IDD1 IDD2 Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Stand-by or Automatic Stand-by) Supply Current (Reset) Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VSS, G = VIH, f = 5MHz E = VDDQ 0.2V, RP = VDDQ 0.2V RP = VSS 0.2V Program in progress VPP = 12V 5% Program in progress VPP = VDD Erase in progress VPP = 12V 5% Erase in progress VPP = VDD E = VDDQ 0.2V, Erase suspended VPP > VDD VPP VDD RP = VSS 0.2V Program in progress VPP = 12V 5% Program in progress VPP = VDD Erase in progress VPP = 12V 5% Erase in progress VPP = VDD -0.5 0.7 VDDQ IOL = 100A, VDD = VDD min, VDDQ = VDDQ min IOH = -100A, VDD = VDD min, VDDQ = VDDQ min VDDQ -0.1 2.7 11.4 3.6 12.6 1 2 1 1 1 1 3 1 9 15 15 5 10 5 10 15 Min Typ Max 1 10 18 50 50 10 20 20 20 50 400 5 5 10 5 10 5 0.8 VDDQ +0.4 0.1 Unit A A mA A A mA mA mA mA A A A A mA A mA A V V V V V V V V
IDD3
Supply Current (Program)
IDD4
Supply Current (Erase)
IDD5 IPP IPP1 IPP2
Supply Current (Program/Erase Suspend) Program Current (Read or Stand-by) Program Current (Read or Stand-by) Program Current (Reset)
IPP3
Program Current (Program)
IPP4
Program Current (Erase)
VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Program Voltage (Program or Erase operations) Program Voltage (Program or Erase operations) Program Voltage (Program and Erase lock-out) VDD Supply Voltage (Program and Erase lock-out)
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M28W320FSU, M28W640FSU
Figure 9. Read AC Waveforms
tAVAV A0-A20/A21(1) tAVQV E tELQV tELQX G tGLQV tGLQX DQ0-DQ15 VALID tGHQX tGHQZ tEHQX tEHQZ VALID tAXQX
ADDR. VALID CHIP ENABLE
OUTPUTS ENABLED
DATA VALID
STANDBY
AI09928
Note: 1. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU.
Table 13. Read AC Characteristics
M28W320FSU Symbol tAVAV tAVQV tAXQX (1) tEHQX (1) tEHQZ (1) tELQV (2) tELQX (1) tGHQX (1) tGHQZ (1) tGLQV (2) tGLQX (1) Alt tRC Parameter 70 Address Valid to Next Address Valid Min Max Min Min Max Max Min Min Max Max Min 70 70 0 0 20 70 0 0 20 20 0 70 70 70 0 0 20 70 0 0 20 20 0 ns ns ns ns ns ns ns ns ns ns ns M28W640FSU Unit
tACC Address Valid to Output Valid tOH tOH tHZ tCE tLZ tOH tDF tOE Address Transition to Output Transition Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid
tOLZ Output Enable Low to Output Transition
Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
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PROGRAM OR ERASE tAVAV VALID tAVWH tWHAX tELWL tWHEH tWHWL tWHGL tWLWH tWHDX COMMAND tVPHWH CMD or DATA STATUS REGISTER tQVVPL tWHEL tELQV CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
AI09929
M28W320FSU, M28W640FSU
A0-A20/A21(1)
E
G
Figure 10. Write AC Waveforms, Write Enable Controlled
W
tDVWH
DQ0-DQ15
VPP
Note: 1. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU.
SET-UP COMMAND
M28W320FSU, M28W640FSU
Table 14. Write AC Characteristics, Write Enable Controlled
M28W320FSU Symbol tAVAV tAVWH tDVWH tELWL tELQV tQVVPL
(1,2)
M28W640FSU Unit 70 70 45 45 0 70 0 200 0 0 0 25 20 25 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Alt tWC tAS tDS tCS Write Cycle Time
Parameter 70 Min Min Min Min Min Min Min Min Min Min Min Min Min Min 70 45 45 0 70 0 200 0 0 0 25 20 25 45
Address Valid to Write Enable High Data Valid to Write Enable High Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Output Valid to VPP Low
tVPHWH
(1)
tVPS tAH tDH tCH
VPP High to Write Enable High Write Enable High to Address Transition Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Output Enable Low
tWHAX tWHDX tWHEH tWHEL tWHGL tWHWL tWLWH
tWPH tWP
Write Enable High to Write Enable Low Write Enable Low to Write Enable High
Note: 1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
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PROGRAM OR ERASE tAVAV VALID tAVEH tEHAX tWLEL tEHWH tEHEL tEHGL tELEH tEHDX COMMAND tVPHEH CMD or DATA STATUS REGISTER tQVVPL tELQV CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
AI09930
M28W320FSU, M28W640FSU
A0-A20/A21
W
G
Figure 11. Write AC Waveforms, Chip Enable Controlled
E
tDVEH
DQ0-DQ15
VPP
Note: 1. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU.
POWER-UP AND SET-UP COMMAND
M28W320FSU, M28W640FSU
Table 15. Write AC Characteristics, Chip Enable Controlled
M28W320FSU Symbol tAVAV tAVEH tDVEH tEHAX tEHDX tEHEL tEHGL tEHWH tELEH tELQV tQVVPL
(1,2)
M28W640FSU Unit 70 70 45 45 0 0 25 25 0 45 70 0 200 0 ns ns ns ns ns ns ns ns ns ns ns ns ns
Alt tWC tAS tDS tAH tDH Write Cycle Time
Parameter 70 Min Min Min Min Min Min Min Min Min Min Min Min Min 70 45 45 0 0 25 25 0 45 70 0 200 0
Address Valid to Chip Enable High Data Valid to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Data Transition
tCPH Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low tWH tCP Chip Enable High to Write Enable High Chip Enable Low to Chip Enable High Chip Enable Low to Output Valid Output Valid to VPP Low tVPS VPP High to Chip Enable High tCS Write Enable Low to Chip Enable Low
tVPHEH
(1)
tWLEL
Note: 1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
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M28W320FSU, M28W640FSU
Figure 12. Power-Up and Reset AC Waveforms
W, E, G
tPHWL tPHEL tPHGL
tPHWL tPHEL tPHGL
RP tVDHPH VDD, VDDQ Power-Up Reset
AI03537b
tPLPH
Table 16. Power-Up and Reset AC Characteristics
Symbol Parameter Test Condition M28W320FSU, M28W640FSU 70 tPHWL tPHEL tPHGL tPLPH(1,2) tVDHPH(3) Reset High to Write Enable Low, Chip Enable Low, Output Enable Low Reset Low to Reset High Supply Voltages High to Reset High During Program and Erase others Min Min Min Min 50 30 100 50 s ns ns s Unit
Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.
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M28W320FSU, M28W640FSU
PACKAGE MECHANICAL
Figure 13. TBGA64 - 10x13 active ball array, 1mm pitch, Bottom View Package Outline
D FD FE D1 SD
E
E1
SE
ddd BALL "A1"
A
e
b A1
A2
BGA-Z23
Note: Drawing is not to scale.
Table 17. TBGA64 - 10x13 active ball array, 1mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd e E E1 FD FE SD SE 1.000 13.000 7.000 1.500 3.000 0.500 0.500 - 12.900 - - - - - 10.000 7.000 0.300 0.800 0.350 9.900 - 0.500 10.100 - 0.100 - 13.100 - - - - - 0.0394 0.5118 0.2756 0.0591 0.1181 0.0197 0.0197 - 0.5079 - - - - - 0.3937 0.2756 0.200 Min Max 1.200 0.350 0.0118 0.0315 0.0138 0.3898 - 0.0197 0.3976 - 0.0039 - 0.5157 - - - - - 0.0079 Typ Min Max 0.0472 0.0138 inches
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M28W320FSU, M28W640FSU
PART NUMBERING
Table 18. Ordering Information Scheme
Example: Device Type M28 Operating Voltage W = VDD = 2.7V to 3.6V; VDDQ = 2.7V to 3.6V Device Function 320FSU = 32 Mbit (2 Mb x16), Uniform Block, Secure, 0.13m 640FSU = 64 Mbit (4 Mb x16), Uniform Block, Secure, 0.13m Speed 70 = 70ns Package ZA = TBGA64:10 x 13mm, 1mm pitch Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-Free and RoHS Package, Standard Packing F = Lead-Free and RoHS Package, Tape & Reel Packing M28W320FSU 70 ZA 6 T
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M28W320FSU, M28W640FSU
Table 19. Daisy Chain Ordering Scheme
Example: Device Type M28W320FSU M28W640FSU Daisy Chain -ZA = TBGA64: 10 x 13, 1mm pitch Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-Free and RoHS Package, Standard Packing F = Lead-Free and RoHS Package, Tape & Reel Packing M28W640FSU -ZA T
Note:Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M28W320FSU, M28W640FSU
APPENDIX A. BLOCK ADDRESS TABLES
Table 20. Block Addresses, M28W320FSU
Block Number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Range 1F0000h-1FFFFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh 100000h-10FFFFh Block Number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Range 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 000000h-00FFFFh
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M28W320FSU, M28W640FSU
Table 21. Block Addresses, M28W640FSU
Block Number 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address Range 3F0000h-3FFFFFh 3E0000h-3EFFFFh 3D0000h-3DFFFFh 3C0000h-3CFFFFh 3B0000h-3BFFFFh 3A0000h-3AFFFFh 390000h-39FFFFh 380000h-38FFFFh 370000h-37FFFFh 360000h-36FFFFh 350000h-35FFFFh 340000h-34FFFFh 330000h-33FFFFh 320000h-32FFFFh 310000h-31FFFFh 300000h-30FFFFh 2F0000h-2FFFFFh 2E0000h-2EFFFFh 2D0000h-2DFFFFh 2C0000h-2CFFFFh 2B0000h-2BFFFFh 2A0000h-2AFFFFh 290000h-29FFFFh 280000h-28FFFFh 270000h-27FFFFh 260000h-26FFFFh 250000h-25FFFFh 240000h-24FFFFh 230000h-23FFFFh 220000h-22FFFFh 210000h-21FFFFh 200000h-20FFFFh Block Number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address Range 1F0000h-1FFFFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh 100000h-10FFFFh 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 000000h-00FFFFh
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M28W320FSU, M28W640FSU
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the data Table 22. Query Structure Overview
Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional)
structure is read from the memory. Tables 22, 23, 24, 25, 26 and 27 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 27., Security Code Area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read command to return to Read mode.
Note: Query data are always presented on the lowest order data outputs.
Table 23. CFI Query Identification String
Offset 00h 01h 02h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0020h 880Ch 8857h Manufacturer Code M28W320FSU Device Code M28W640FSU Device Code Description Value ST Uniform
reserved Reserved 0051h 0052h 0059h 0003h 0000h 0035h Address for Primary Algorithm extended Query table (see Table 26.) 0000h 0000h 0000h 0000h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor specified algorithm supported (0000h means none exists) Address for Alternate Algorithm extended Query table (0000h means none exists) NA P = 35h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Query Unique ASCII String "QRY" "Q" "R" "Y" Intel compatible
NA
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'.
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M28W320FSU, M28W640FSU
Table 24. CFI Query System Interface Information
Offset 1Bh Data 0027h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100mV VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100mV VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100mV VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100mV Typical time-out per single word program = 2n s Typical time-out for Double/Quadruple Word Program = 2n s Typical time-out per individual block erase = 2n ms Typical time-out for full chip erase = 2n ms Maximum time-out for Word program = 2n times typical Maximum time-out for Double/Quadruple Word Program = 2n times typical Maximum time-out per individual block erase = 2n times typical Maximum time-out for chip erase = 2n times typical Value 2.7V
1Ch
0036h
3.6V
1Dh
00B4h
11.4V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
00C6h 0004h 0004h 000Ah 0000h 0005h 0005h 0003h 0000h
12.6V 16s 16s 1s NA 512s 512s 8s NA
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M28W320FSU, M28W640FSU
Table 25. Device Geometry Definition
Offset Word Mode M28W640FSU M28W320FSU Data Description Value
0016h
4 MBytes
27h
Device Size = 2n in number of bytes
0017h
8 MBytes
28h 29h 2Ah 2Bh 2Ch M28W640FSU M28W320FSU 2Dh 2Eh 2Fh 30h 2Dh 2Eh 2Fh 30h
0001h 0000h 0003h 0000h 0001h 001Fh 0000h 0000h 0002h 003Fh 0000h 0000h 0002h
Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions within the device. It specifies the number of regions within the device containing contiguous Erase Blocks of the same size. Region 1 Information Number of identical-size erase blocks = 001Fh+1 Region 1 Information Block size in Region 1 = 0200h * 256 byte Region 1 Information Number of identical-size erase blocks = 003Fh+1 Region 1 Information Block size in Region 1 = 0200h * 256 byte Reserved
x16 Async. 8
1
32 128 KBytes 64 128 KBytes
31h to 34h
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M28W320FSU, M28W640FSU
Table 26. Primary Algorithm-Specific Extended Query Table
Offset P = 35h (1) (P+0)h = 35h (P+1)h = 36h (P+2)h = 37h (P+3)h = 38h (P+4)h = 39h (P+5)h = 3Ah (P+6)h = 3Bh (P+7)h = 3Ch (P+8)h = 3Dh Data 0050h 0052h 0049h 0031h 0030h 0066h 0000h 0000h 0000h Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. bit 0Chip Erase supported(1 = Yes, 0 = No) bit 1Suspend Erase supported(1 = Yes, 0 = No) bit 2Suspend Program supported(1 = Yes, 0 = No) bit 3Legacy Lock/Unlock supported(1 = Yes, 0 = No) bit 4Queued Erase supported(1 = Yes, 0 = No) bit 5Instant individual block locking supported(1 = Yes, 0 = No) bit 6Protection bits supported(1 = Yes, 0 = No) bit 7Page mode read supported(1 = Yes, 0 = No) bit 8Synchronous read supported(1 = Yes, 0 = No) bit 31 to 9 Reserved; undefined bits are `0' Supported Functions after Suspend Read Array, Read Status Register and CFI Query are always supported during Erase or Program operation bit 0Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1Reserved; undefined bits are `0' Block Lock Status Defines which bits in the Block Status Register section of the Query are implemented. Address (P+A)h contains less significant byte bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No) bit 15 to 1Reserved for future use; undefined bits are `0' VDD Logic Supply Optimum Program/Erase voltage (highest performance) bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100mV VPP Supply Optimum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100mV Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) Protection Register bytes. Some are pre-programmed with device unique serial numbers. Others are user programmable. Bits 0-15 point to the Protection Register Lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bit 0 to 7 Lock/bytes JEDEC-plane physical low address bit 8 to 15Lock/bytes JEDEC-plane physical high address bit 16 to 23 "n" such that 2n = factory pre-programmed bytes bit 24 to 31 "n" such that 2n = user programmable bytes Reserved Primary Algorithm extended Query table unique ASCII string "PRI" Description Value "P" "R" "I" "1" "0"
No Yes Yes No No Yes Yes No No
(P+9)h = 3Eh
0001h
Yes
(P+A)h = 3Fh (P+B)h = 40h
0003h 0000h
Yes 3V
(P+C)h = 41h
0030h
(P+D)h = 42h
00C0h
12V
(P+E)h = 43h (P+F)h = 44h (P+10)h = 45h (P+11)h = 46h (P+12)h = 47h
0001h 0080h 0000h 0003h 0004h
01 80h 00h 8 Bytes 16 Bytes
(P+13)h = 48h
Note: 1. See Table 23., offset 15 for P pointer definition.
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M28W320FSU, M28W640FSU
Table 27. Security Code Area
Offset 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch Data 00XX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 128 bits: User Programmable OTP 64 bits: unique device number Protection Register Lock Description
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M28W320FSU, M28W640FSU
APPENDIX C. FLOWCHARTS AND PSEUDO CODES
Figure 14. Program Flowchart and Pseudo Code
Start
Write 40h or 10h
program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10) ; */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Write Address & Data
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI03538b
Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M28W320FSU, M28W640FSU
Figure 15. Double Word Program Flowchart and Pseudo Code
Start
Write 30h
Write Address 1 & Data 1 (3)
Write Address 2 & Data 2 (3)
double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (any_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI03539b
Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
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M28W320FSU, M28W640FSU
Figure 16. Quadruple Word Program Flowchart and Pseudo Code
Start
Write 56h
Write Address 1 & Data 1 (3)
quadruple_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) { writeToFlash (any_address, 0x56) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */
Write Address 2 & Data 2 (3)
writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ writeToFlash (addressToProgram3, dataToProgram3) ; /*see note (3) */ writeToFlash (addressToProgram4, dataToProgram4) ; /*see note (3) */
Write Address 3 & Data 3 (3)
Write Address 4 & Data 4 (3)
/*Memory enters read status state after the Program command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06233
Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
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M28W320FSU, M28W640FSU
Figure 17. Program Suspend & Resume Flowchart and Pseudo Code
Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Write B0h
Read Status Register
b7 = 1 YES b2 = 1 YES Write FFh
NO
} while (status_register.b7== 0) ;
NO
Program Complete
if (status_register.b2==0) /*program completed */ { writeToFlash (any_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another address
} else { writeToFlash (any_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } } Read Data
Write D0h
Write FFh
Program Continues
AI03540b
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M28W320FSU, M28W640FSU
Figure 18. Erase Flowchart and Pseudo Code
Start erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ; writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */
Write 20h
Write Block Address & D0h
Read Status Register
do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
b7 = 1
NO } while (status_register.b7== 0) ;
YES b3 = 0 YES b4, b5 = 1 NO b5 = 0 YES b1 = 0 YES End }
AI03541b
NO
VPP Invalid Error (1)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
YES
Command Sequence Error (1)
if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ;
NO
Erase Error (1)
if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ;
NO
Erase to Protected Block Error (1)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.
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M28W320FSU, M28W640FSU
Figure 19. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
erase_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; /* read status register to check if erase has already completed */
Write 70h
Read Status Register
do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
b7 = 1 YES b6 = 1 YES Write FFh
NO
} while (status_register.b7== 0) ;
NO
Erase Complete
if (status_register.b6==0) /*erase completed */ { writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock else
} { writeToFlash (any_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume erase*/ } }
Write D0h
Write FFh
Erase Continues
Read Data
AI03542b
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Figure 20. Protection Register Program Flowchart and Pseudo Code
Start
Write C0h
protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0xC0) ;
Write Address & Data
writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI04381
Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M28W320FSU, M28W640FSU
APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE
Table 28. Write State Machine Current/Next, sheet 1 of 2.
Current State Read Array Read Status Read Elect.Sg. Read CFI Query Prot. Prog. Setup Prot. Prog. (continue) Prot. Prog. (complete) Prog. Setup Program (continue) Prog. Sus Status Prog. Sus Read Array Prog. Sus Read Elect.Sg. Prog. Sus Read CFI Program (complete) Erase Setup Erase Cmd.Error Erase (continue) Erase Sus Read Sts Erase Sus Read Array Erase Sus Read Elect.Sg. Erase Sus Read CFI Erase (complete) SR bit 7 "1" "1" "1" "1" "1" "0" "1" "1" "0" "1" "1" Data When Read Array Status Command Input (and Next State) Read Array (FFh) Program Setup (10/40h) Program Setup Program Setup Program Setup Erase Setup (20h) Ers. Setup Erase Setup Erase Setup Erase Setup Erase Confirm (D0h) Prog/Ers Suspend (B0h) Read Array Read Array Read Array Read Array Protection Register Program Protection Register Program continue Read Array Program Setup Erase Setup Read Array Program Program (continue) Prog. Sus Read Array Prog. Sus Read Array Program Suspend to Read Array Program Suspend to Read Array Program Suspend to Read Array Program Suspend to Read Array Program Setup Erase Setup Erase (continue) Program (continue) Program (continue) Program (continue) Program (continue) Prog. Sus Read Sts Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Read Array Erase CmdError Read Array Erase Sus Read Sts Erase (continue) Erase (continue) Erase (continue) Erase (continue) Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Read Array Erase (continue) Program (continue) Program (continue) Program (continue) Program (continue) Program (continue) Prog. Sus Read Sts Prog. Sus Read Sts Prog. Sus Read Sts Prog. Sus Read Sts Read Status Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Read Array Read Status Read Array Prog/Ers Resume (D0h) Read Status (70h) Read Sts. Read Status Read Status Read Status Clear Status (50h) Read Array Read Array Read Array Read Array
Read Array Prog.Setup Read Array
Electronic Read Array Signature CFI Status Status Status Status Status Status Array Read Array
"1"
Electronic Prog. Sus Signature Read Array CFI Status Status Status Status Status Array Erase Sus Read Array Erase Sus Read Array Prog. Sus Read Array Read Array
"1" "1" "1" "1" "0" "1" "1"
Erase Command Error Read Array Program Setup Erase Setup
Erase Command Error Read Status Read Array
Erase (continue) Program Setup Program Setup Program Setup Program Setup Program Setup Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Erase Setup
Erase (continue) Erase (continue) Erase (continue) Erase (continue) Erase (continue) Erase Sus Erase Sus Read Sts Read Array Erase Sus Erase Sus Read Sts Read Array Erase Sus Erase Sus Read Sts Read Array Erase Sus Erase Sus Read Sts Read Array Read Status Read Array
"1"
Electronic Erase Sus Signature Read Array CFI Status Erase Sus Read Array Read Array
"1" "1"
Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.
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M28W320FSU, M28W640FSU
Table 29. Write State Machine Current/Next, sheet 2 of 2.
Command Input (and Next State) Current State Read Array Read Status Read Elect.Sg. Read CFI Query Prot. Prog. Setup Prot. Prog. (continue) Prot. Prog. (complete) Prog. Setup Program (continue) Prog. Suspend Read Status Prog. Suspend Read Array Prog. Suspend Read Elect.Sg. Prog. Suspend Read CFI Program (complete) Erase Setup Erase Cmd.Error Erase (continue) Erase Suspend Read Ststus Erase Suspend Read Array Erase Suspend Read Elect.Sg. Erase Suspend Read CFI Query Erase (complete) Erase Suspend Read Elect.Sg. Erase Suspend Read Elect.Sg. Erase Suspend Read Elect.Sg. Erase Suspend Read Elect.Sg. Read Elect.Sg. Read Elect.Sg. Prog. Suspend Read Elect.Sg. Prog. Suspend Read Elect.Sg. Prog. Suspend Read Elect.Sg. Prog. Suspend Read Elect.Sg. Read Elect.Sg. Read Elect.Sg. Read Elect.Sg. (90h) Read Elect.Sg. Read Elect.Sg. Read Elect.Sg. Read Elect.Sg. Read CFI Query (98h) Read CFI Query Read CFI Query Read CFI Query Read CFI Query Protection Register Program Protection Register Program (continue) Read CFI Query Program Program (continue) Prog. Suspend Read CFI Query Prog. Suspend Read CFI Query Prog. Suspend Read CFI Query Prog. Suspend Read CFI Query Read CFIQuery Erase Command Error Read CFI Query Erase (continue) Erase Suspend Read CFI Query Erase Suspend Read CFI Query Erase Suspend Read CFI Query Erase Suspend Read CFI Query Read CFI Query Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array Prot. Prog. Setup Prot. Prog. Setup Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup (C0h) Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup
Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.
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M28W320FSU, M28W640FSU
REVISION HISTORY
Table 30. Document Revision History
Date 07-Dec-2004 07-Feb-2005 16-May-2005 Version 0.1 0.2 1.0 First Issue. Locations 31h to 34h set to reserved in Table 25., Device Geometry Definition. Datasheet status updated to "Full Datasheet". Table 25., Device Geometry Definition updated. Revision Details
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M28W320FSU, M28W640FSU
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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